november 2013 FQD19N10 n-channel qfet ? mosfet 100 v, 15.6 a, 100 m description FQD19N10 n-channel qfet ? mosfet ?2007 fairchild semiconductor corporation FQD19N10 rev. c1 www.fairchildsemi.com 1 this n-channel enhancement mode power mosfet is produced using fairchild semiconductors proprietary planar stripe and dmos technology. this advanced mosfet technology has been especially tailored to reduce on-state resistance, and to provide superior switching performance and high avalanche energy strength. these devices are suitable for switched mode power supplies, audio am plifier, dc motor control, and variable switching power applications. features absolute maximum ratings t c = 25 o c unless otherwise noted. thermal characteristics symbol parameter fq d19 n10 tm unit r ? jc thermal resistance, junction to case, max. 2.5 o c/w r ? ja thermal resistance, j unction to ambi ent ( m inimum p ad of 2-oz copper), max. 110 thermal resistance, junction to ambient (*1 in 2 pad of 2-oz copper), max. 50 ? 15.6 a, 100 v, r ds(on) = 100 m? (max.) @ v gs = 10 v, i d = 7.8 a ? low gate charge (typ. 19 nc) ? low crss (typ. 32 pf) ? 100% avalanche tested d-pak g s d g s d symbol parameter FQD19N10tm unit v dss drain-source voltage 100 v i d drain current - continuous (t c = 25c) 15.6 a - continuous (t c = 100c) 9.8 a i dm drain current - pulsed (note 1) 62.4 a v gss gate-source voltage ? 25 v e as single pulsed avalanche energy (note 2) 220 mj i ar avalanche current (note 1) 15.6 a e ar repetitive avalanche energy (note 1) 5.0 mj dv/dt peak diode recovery dv/dt (note 3) 6.0 v/ns p d power dissipation (t a = 25c) * 2.5 w power dissipation (t c = 25c) 50 w - derate above 25c 0.4 w/c t j , t stg operating and storage temperature range -55 to +150 c t l maximum lead temperature for soldering, 1/8" from case for 5 seconds 300 c
package marking and ordering information part number top mark package reel size tape width quantity FQD19N10 FQD19N10tm d-pak 330 mm 16 mm 2500 units FQD19N10 n-channel qfet ? mosfet ?2007 fairchild semiconductor corporation FQD19N10 rev. c1 www.fairchildsemi.com 2 1. repetitive rating : p ulse- width limited by m aximum junction temperature. 2. l = 1.35 mh, i as = 15.6 a, v dd = 25 v, r g = 25 ? , starting t j = 25 o c. 3. i sd 19 a, di/dt 300 a/s, v dd bv dss , s tarting t j = 25 o c. 4. essentially independent of operating temperature. packing method tape and reel electrical characteristics t c = 25 o c unless otherwise noted. symbol parameter test conditions min. typ. max. unit ? off characteristics bv dss drain-source breakdown voltage v gs = 0 v, i d = 250 ? a 100 -- -- v ? bv dss / ? t j breakdown voltage temperature coefficient i d = 250 ? a, referenced to 25c -- 0.1 -- v/c i dss zero gate voltage drain current v ds = 100 v, v gs = 0 v -- -- 1 ? a v ds = 80 v, t c = 125c -- -- 10 ? a i gssf gate-body leakage current, forward v gs = 25 v, v ds = 0 v -- -- 100 na i gssr gate-body leakage current, reverse v gs = -25 v, v ds = 0 v -- -- -100 na ? on characteristics v gs(th) gate threshold voltage v ds = v gs , i d = 250 ? a 2.0 -- 4.0 v r ds(on) static drain-source on-resistance v gs = 10 v, i d = 7.8 a -- 0.078 0.1 ? g fs forward transconductance v ds = 40 v, i d = 7.8 a -- 11 -- s ? dynamic characteristics c iss input capacitance v ds = 25 v, v gs = 0 v, f = 1.0 mhz (note 4) -- 600 780 pf c oss output capacitance -- 165 215 pf c rss reverse transfer capacitance -- 32 40 pf ? switching characteristics t d(on) turn-on delay time v dd = 50 v, i d = 19 a, r g = 25 ? -- 7.5 25 ns t r turn-on rise time -- 150 310 ns t d(off) turn-off delay time -- 20 50 ns t f turn-off fall time -- 65 140 ns q g total gate charge v ds = 80 v, i d = 19 a, v gs = 10 v (note 4) -- 19 25 nc q gs gate-source charge -- 3.9 -- nc q gd gate-drain charge -- 9.0 -- nc drain-source diode characteristics and maximum ratings i s maximum continuous drain-source diode forward current -- -- 15.6 a i sm maximum pulsed drain-source diode forward current -- -- 62.4 a v sd drain-source diode forward voltage v gs = 0 v, i s = 15.6 a -- -- 1.5 v t rr reverse recovery time v gs = 0 v, i s = 19 a, di f / dt = 100 a/ ? s -- 78 -- ns q rr reverse recovery charge -- 200 -- nc
FQD19N10 n-channel qfet ? mosfet ?2007 fairchild semiconductor corporation FQD19N10 rev. c1 www.fairchildsemi.com 3 ! 0481 21 62 0 0 2 4 6 8 10 12 v ds = 50v v ds = 80v note : i d = 19a v gs , gate-source voltage [v] q g , total gate charge [nc] 10 -1 0 10 1 0 300 600 900 1200 1500 c iss = c gs + c gd (c ds = shorted) c oss = c ds + c gd c rss = c gd notes : 1. v gs = 0 v 2. f = 1 mhz c rss c oss c iss capacitance [pf] 10 v ds , drain-source voltage [v] 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 10 -1 10 0 10 1 25 150 notes : 1. v gs = 0v 2. 250 s pulse test i dr , reverse drain current [a] v sd , source-drain voltage [v] 0 0 2 4 0 0 6 0 8 0.00 0.06 0.12 0.18 0.24 0.30 note : t j = 25 v gs = 20v v gs = 10v r ds(on) [ ? ], drain-source on-resistance i d , drain current [a] 4 2 681 0 10 -1 10 0 10 1 notes : 1. v ds = 40v 2. 250 s pulse test -55 150 25 i d , drain current [a] v gs , gate-source voltage [v] 10 -1 0 10 1 10 0 10 1 v gs top : 15.0 v 10.0 v 8.0 v 7.0 v 6.0 v 5.5 v 5.0 v bottom : 4.5 v notes : 1. 250 s pulse test 2. t c = 25 i d , drain current [a] 10 v ds , drain-source voltage [v] figure 5. capacitance characteristics figu re 6. gate charge characteristics figure 3. on-resistance variation vs. drain current and gate voltage figure 4. body diode forward voltage variation vs. source current and temperature figure 2. transfer characteristics figure 1. on-region characteristics
FQD19N10 n-channel qfet ? mosfet ?2007 fairchild semiconductor corporation FQD19N10 rev. c1 www.fairchildsemi.com 4 !
z ? jc (t), thermal response [ o c/w] 10 -5 10 -4 10 -3 10 -2 10 1- 10 0 10 1 10 -2 10 -1 10 0 n o te s : /w m ax. 1. z jc (t) = 2.5 2. d u ty f a ctor, d = t 1 /t 2 3. t jm - t c = p dm * z jc (t) single pulse d=0.5 0.02 0.2 0.05 0.1 0.01 25 50 75 100 125 150 0 4 8 12 16 i d , drain current [a] t c , case temperature [ ] 10 0 10 1 10 2 10 -1 10 0 10 1 10 2 10 ? s dc 10 ms 1 ms 100 ? s operation in this area is limited by r ds(on) notes : 1. t c = 25 o c 2. t j = 150 o c 3. single pulse i d , drain current [a] -100 -50 0 50 100 150 200 0.0 0.5 1.0 1.5 2.0 2.5 3.0 notes : 1. v gs = 10 v 2. i d = 7.8 a r ds(on) , (normalized) drain-source on-resistance t j , junction temperature [ o c] -100 -50 0 50 100 150 200 0.8 0.9 1.0 1.1 1.2 notes : 1. v gs = 0 v 2. i d = 250 a bv dss , (normalized) drain-source breakdown voltage t j , junction temperature [ o c] v ds , drain-source voltage [v] figure 9. maximum safe operating area figure 10. maximum drain current vs. case temperature figure 7. breakdown voltage variation vs. temperature figure 8. on-resistance variation vs. temperature t 1 , rectangular p ulse d uration [sec] figure 11. transient thermal response curve t 1 p dm t 2
figure 12. gate charge test circuit & waveform f igure 13 . resistive switc hing test circuit & waveforms figure 14 . unclamped inductive switching test circuit & waveforms v gs v ds 10% 90% t d(on) t r t on t off t d(off) t f v dd 10v v ds r l dut r g v gs v gs v ds 10% 90% t d(on) t r t on t off t d(off) t f v dd 10v v ds r l dut r g v gs v gs charge v gs 10v q g q gs q gd 3ma v gs dut v ds 300nf 50k 200nf 12v same type as dut charge v gs 10v q g q gs q gd 3ma v gs dut v ds 300nf 50k 200nf 12v same type as dut e as =li as 2 ---- 2 1 -------------------- bv dss -v dd bv dss v dd v ds bv dss t p v dd i as v ds (t) i d (t) time 10v dut r g l i d t p e as =li as 2 ---- 2 1 e as =li as 2 ---- 2 1 ---- 2 1 -------------------- bv dss -v dd bv dss v dd v ds bv dss t p v dd i as v ds (t) i d (t) time 10v dut r g l l i d i d t p v gs v gs i g = const. ?2007 fairchild semiconductor corporation FQD19N10 rev. c1 www.fairchildsemi.com 5 FQD19N10 n-channel qfet ? mosfet
f igure 15. pe ak diode recovery dv/dt test circuit & waveforms dut v ds + _ driver r g same type as dut v gs ? dv/dt controlled by r g ?i sd controlled by pulse period v dd l i sd 10v v gs ( driver ) i sd ( dut ) v ds ( dut ) v dd body diode forward voltage drop v sd i fm , body diode forward current body diode reverse current i rm body diode recovery dv/dt di/dt d = gate pulse width gate pulse period -------------------------- dut v ds + _ driver r g same type as dut v gs ? dv/dt controlled by r g ?i sd controlled by pulse period v dd l l i sd 10v v gs ( driver ) i sd ( dut ) v ds ( dut ) v dd body diode forward voltage drop v sd i fm , body diode forward current body diode reverse current i rm body diode recovery dv/dt di/dt d = gate pulse width gate pulse period -------------------------- d = gate pulse width gate pulse period -------------------------- FQD19N10 n-channel qfet ? mosfet ?2007 fairchild semiconductor corporation FQD19N10 rev. c1 www.fairchildsemi.com 6
?2007 fairchild semiconductor corporation FQD19N10 rev. c1 www.fairchildsemi.com 7 FQD19N10 n-channel qfet ? mosfet mechanical dimensions figure 16. to252 (d-pak), molded, 3-lead, option aa&ab package drawings are provided as a service to customers considering fairchild com ponents. drawings may change in any manner without notice. please note the revision and/or date on the draw ing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specif- ically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packag ing area for the most recent package drawings: http://www.fairchildsemi.com/package/packagedetails.html?id=pn_tt252-003
?2007 fairc hild semiconductor corporation FQD19N10 rev. c1 www.fairchildsemi.com 8 trademarks the following includes registered and unregistered trademarks and service marks, owned by fairchild semiconductor and/or its gl obal subsidiaries, and is not intended to be an exhaustive list of all such trademarks. *trademarks of system general corporation, used under license by fairchild semiconductor. disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function, or desi gn. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. these specifications do not expand the terms of fairchilds worldwide terms and conditio ns, specifically the warranty therein, which covers these products. life support policy fairchilds products are not authorized for use as critical components in life support de vices or systems without the express written approval of fai rchild semiconductor corporation. as used here in: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms accupower? 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FQD19N10 n-channel qfet ? mosfet
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